1. Field of the Invention
The present invention relates to interconnection layout of a nonvolatile semiconductor memory.
2. Description of the Related Art
Recently, a nonvolatile semiconductor memory, particularly a NAND flash memory is used in various electronic devices while exploiting large-capacity and nonvolatile characteristics.
In the case of the NAND flash memory, a cell unit includes plural memory cells connected in series and two select gate transistors connected on both ends of the plural memory cells. The cell unit is called NAND string.
When downsizing is performed in the memory cell and gate select transistor with increasing capacity, a resistance of a conductive line becomes troublesome unless means for using the conductive line disposed on a memory cell array and a method of connecting the conductive lines are properly devised.
For example, for a cell source line connected to a source diffusion layer on one end of the cell unit, and for a cell well line connected to a cell well area where the memory cell and the select gate transistor are arranged, it is necessary that the resistance of the cell source line and the cell well line be lowered as much as possible to stabilize potentials of the source diffusion layer and cell well area.
U.S. 2006/0198196 (Sep. 7, 2006) discloses a technique in which one (uppermost layer) of plural metal layers disposed on the memory cell array is maximally utilized for the cell source line and cell well line to lower the resistance of the conductive lines.